fdbe1442c5
With GCC 4.9, the MIPS NDK toolchain has been changed to only support 16 spregs by default - the even-numbered ones. This has been changed to support the R6 MIPS architecture. While the old behaviour could be restored by adding "-modd-spreg", this would come with a performance hit because the kernel would emulate odd-numbered spregs and missing R2 instructions. As a result of this change, the functions removed in this CL no longer compile as there are no longer enough spregs for the compiler to assign. So we are removing these functions and they will use the C implementation until the MIPS code is rewritten. R=andrew@webrtc.org, ljubomir.papuga@gmail.com, pasko@chromium.org Review URL: https://webrtc-codereview.appspot.com/16159005 Patch from Fabrice de Gans-Riberi <fdegans@chromium.org>. git-svn-id: http://webrtc.googlecode.com/svn/trunk@6797 4adac7df-926f-26a2-2b94-8c16560cd09d
336 lines
7.0 KiB
C
336 lines
7.0 KiB
C
/*
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* Copyright (c) 2014 The WebRTC project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "webrtc/modules/audio_processing/aec/aec_rdft.h"
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#include "webrtc/typedefs.h"
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static void bitrv2_128_mips(float *a) {
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// n is 128
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float xr, xi, yr, yi;
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xr = a[8];
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xi = a[9];
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yr = a[16];
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yi = a[17];
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a[8] = yr;
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a[9] = yi;
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a[16] = xr;
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a[17] = xi;
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xr = a[64];
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xi = a[65];
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yr = a[2];
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yi = a[3];
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a[64] = yr;
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a[65] = yi;
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a[2] = xr;
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a[3] = xi;
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xr = a[72];
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xi = a[73];
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yr = a[18];
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yi = a[19];
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a[72] = yr;
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a[73] = yi;
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a[18] = xr;
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a[19] = xi;
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xr = a[80];
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xi = a[81];
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yr = a[10];
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yi = a[11];
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a[80] = yr;
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a[81] = yi;
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a[10] = xr;
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a[11] = xi;
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xr = a[88];
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xi = a[89];
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yr = a[26];
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yi = a[27];
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a[88] = yr;
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a[89] = yi;
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a[26] = xr;
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a[27] = xi;
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xr = a[74];
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xi = a[75];
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yr = a[82];
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yi = a[83];
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a[74] = yr;
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a[75] = yi;
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a[82] = xr;
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a[83] = xi;
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xr = a[32];
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xi = a[33];
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yr = a[4];
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yi = a[5];
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a[32] = yr;
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a[33] = yi;
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a[4] = xr;
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a[5] = xi;
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xr = a[40];
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xi = a[41];
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yr = a[20];
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yi = a[21];
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a[40] = yr;
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a[41] = yi;
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a[20] = xr;
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a[21] = xi;
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xr = a[48];
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xi = a[49];
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yr = a[12];
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yi = a[13];
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a[48] = yr;
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a[49] = yi;
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a[12] = xr;
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a[13] = xi;
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xr = a[56];
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xi = a[57];
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yr = a[28];
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yi = a[29];
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a[56] = yr;
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a[57] = yi;
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a[28] = xr;
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a[29] = xi;
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xr = a[34];
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xi = a[35];
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yr = a[68];
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yi = a[69];
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a[34] = yr;
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a[35] = yi;
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a[68] = xr;
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a[69] = xi;
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xr = a[42];
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xi = a[43];
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yr = a[84];
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yi = a[85];
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a[42] = yr;
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a[43] = yi;
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a[84] = xr;
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a[85] = xi;
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xr = a[50];
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xi = a[51];
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yr = a[76];
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yi = a[77];
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a[50] = yr;
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a[51] = yi;
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a[76] = xr;
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a[77] = xi;
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xr = a[58];
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xi = a[59];
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yr = a[92];
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yi = a[93];
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a[58] = yr;
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a[59] = yi;
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a[92] = xr;
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a[93] = xi;
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xr = a[44];
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xi = a[45];
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yr = a[52];
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yi = a[53];
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a[44] = yr;
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a[45] = yi;
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a[52] = xr;
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a[53] = xi;
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xr = a[96];
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xi = a[97];
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yr = a[6];
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yi = a[7];
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a[96] = yr;
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a[97] = yi;
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a[6] = xr;
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a[7] = xi;
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xr = a[104];
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xi = a[105];
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yr = a[22];
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yi = a[23];
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a[104] = yr;
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a[105] = yi;
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a[22] = xr;
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a[23] = xi;
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xr = a[112];
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xi = a[113];
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yr = a[14];
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yi = a[15];
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a[112] = yr;
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a[113] = yi;
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a[14] = xr;
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a[15] = xi;
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xr = a[120];
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xi = a[121];
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yr = a[30];
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yi = a[31];
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a[120] = yr;
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a[121] = yi;
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a[30] = xr;
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a[31] = xi;
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xr = a[98];
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xi = a[99];
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yr = a[70];
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yi = a[71];
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a[98] = yr;
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a[99] = yi;
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a[70] = xr;
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a[71] = xi;
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xr = a[106];
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xi = a[107];
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yr = a[86];
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yi = a[87];
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a[106] = yr;
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a[107] = yi;
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a[86] = xr;
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a[87] = xi;
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xr = a[114];
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xi = a[115];
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yr = a[78];
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yi = a[79];
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a[114] = yr;
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a[115] = yi;
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a[78] = xr;
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a[79] = xi;
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xr = a[122];
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xi = a[123];
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yr = a[94];
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yi = a[95];
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a[122] = yr;
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a[123] = yi;
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a[94] = xr;
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a[95] = xi;
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xr = a[100];
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xi = a[101];
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yr = a[38];
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yi = a[39];
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a[100] = yr;
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a[101] = yi;
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a[38] = xr;
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a[39] = xi;
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xr = a[108];
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xi = a[109];
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yr = a[54];
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yi = a[55];
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a[108] = yr;
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a[109] = yi;
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a[54] = xr;
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a[55] = xi;
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xr = a[116];
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xi = a[117];
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yr = a[46];
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yi = a[47];
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a[116] = yr;
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a[117] = yi;
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a[46] = xr;
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a[47] = xi;
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xr = a[124];
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xi = a[125];
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yr = a[62];
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yi = a[63];
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a[124] = yr;
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a[125] = yi;
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a[62] = xr;
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a[63] = xi;
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xr = a[110];
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xi = a[111];
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yr = a[118];
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yi = a[119];
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a[110] = yr;
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a[111] = yi;
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a[118] = xr;
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a[119] = xi;
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}
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static void cftfsub_128_mips(float *a) {
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float x0r, x0i, x1r, x1i, x2r, x2i, x3r, x3i;
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float f0, f1, f2, f3, f4, f5, f6, f7;
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int tmp_a, count;
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cft1st_128(a);
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cftmdl_128(a);
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__asm __volatile (
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".set push \n\t"
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".set noreorder \n\t"
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"addiu %[tmp_a], %[a], 0 \n\t"
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"addiu %[count], $zero, 16 \n\t"
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"1: \n\t"
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"addiu %[count], %[count], -1 \n\t"
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"lwc1 %[f0], 0(%[tmp_a]) \n\t"
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"lwc1 %[f1], 4(%[tmp_a]) \n\t"
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"lwc1 %[f2], 128(%[tmp_a]) \n\t"
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"lwc1 %[f3], 132(%[tmp_a]) \n\t"
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"lwc1 %[f4], 256(%[tmp_a]) \n\t"
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"lwc1 %[f5], 260(%[tmp_a]) \n\t"
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"lwc1 %[f6], 384(%[tmp_a]) \n\t"
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"lwc1 %[f7], 388(%[tmp_a]) \n\t"
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"add.s %[x0r], %[f0], %[f2] \n\t"
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"add.s %[x0i], %[f1], %[f3] \n\t"
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"add.s %[x2r], %[f4], %[f6] \n\t"
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"add.s %[x2i], %[f5], %[f7] \n\t"
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"sub.s %[x1r], %[f0], %[f2] \n\t"
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"sub.s %[x1i], %[f1], %[f3] \n\t"
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"sub.s %[x3r], %[f4], %[f6] \n\t"
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"sub.s %[x3i], %[f5], %[f7] \n\t"
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"add.s %[f0], %[x0r], %[x2r] \n\t"
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"add.s %[f1], %[x0i], %[x2i] \n\t"
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"sub.s %[f4], %[x0r], %[x2r] \n\t"
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"sub.s %[f5], %[x0i], %[x2i] \n\t"
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"sub.s %[f2], %[x1r], %[x3i] \n\t"
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"add.s %[f3], %[x1i], %[x3r] \n\t"
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"add.s %[f6], %[x1r], %[x3i] \n\t"
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"sub.s %[f7], %[x1i], %[x3r] \n\t"
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"swc1 %[f0], 0(%[tmp_a]) \n\t"
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"swc1 %[f1], 4(%[tmp_a]) \n\t"
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"swc1 %[f2], 128(%[tmp_a]) \n\t"
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"swc1 %[f3], 132(%[tmp_a]) \n\t"
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"swc1 %[f4], 256(%[tmp_a]) \n\t"
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"swc1 %[f5], 260(%[tmp_a]) \n\t"
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"swc1 %[f6], 384(%[tmp_a]) \n\t"
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"swc1 %[f7], 388(%[tmp_a]) \n\t"
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"bgtz %[count], 1b \n\t"
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" addiu %[tmp_a], %[tmp_a], 8 \n\t"
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".set pop \n\t"
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: [f0] "=&f" (f0), [f1] "=&f" (f1), [f2] "=&f" (f2), [f3] "=&f" (f3),
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[f4] "=&f" (f4), [f5] "=&f" (f5), [f6] "=&f" (f6), [f7] "=&f" (f7),
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[x0r] "=&f" (x0r), [x0i] "=&f" (x0i), [x1r] "=&f" (x1r),
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[x1i] "=&f" (x1i), [x2r] "=&f" (x2r), [x2i] "=&f" (x2i),
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[x3r] "=&f" (x3r), [x3i] "=&f" (x3i), [tmp_a] "=&r" (tmp_a),
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[count] "=&r" (count)
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: [a] "r" (a)
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: "memory"
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);
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}
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void aec_rdft_init_mips(void) {
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cftfsub_128 = cftfsub_128_mips;
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bitrv2_128 = bitrv2_128_mips;
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}
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